1. Field of the Invention
The invention relates generally to the field of semiconductor device manufacturing and, more particularly, to methods for depositing nickel and forming metal silicide and germanide.
2. Description of the Related Art
In forming advanced semiconductor devices, part of the silicon that is present in gate, source and drain structures can be converted into low-resistivity metal silicides. This is done to realize a conductive path with a low bulk resistivity on the one hand, and to ensure a good contact resistance on the other hand. In the past, TiSi2 was used for this process; then later CoSi2 was the silicide of choice for the most advanced devices. As both TiSi2 and CoSi2 consume a relatively large amount of silicon, there has been a switch to using NiSix to form these conductive paths. This silicide combines a low bulk resistivity with a relatively low amount of silicon consumption.
A process of forming NiSix on a substrate 80 is depicted in FIGS. 1A-1D. First, the basic structure of the transistor is formed, including a gate electrode 10, a gate dielectric 20, a source 30 and a drain 40 (FIG. 1A). On the sides of the polycrystalline silicon (poly-Si) gate, sidewall spacers 50 are deposited to insulate the sidewalls of the poly-Si/gate oxide stack from films that are subsequently formed and facilitate self-aligned doping of the source/drain regions 30/40. A nickel film 60 (Ni) is then deposited, usually through a physical vapor deposition (PVD, e.g., sputtering) process (FIG. 1B). The wafer is heated to a temperature at which the Ni reacts with the underlying Si to form nickel silicide (NiSix) 70. Depending on the anneal temperature, NiSix as used herein can represent Ni2Si, NiSi, NiSi2 and/or a mixture thereof. The temperature is typically kept low enough (e.g., <about 600° C.) to inhibit formation of NiSi2, which has a relatively high resistivity.
In principle, nickel silicide (NiSix) forms in a self-aligned fashion, i.e., only at locations where Ni and Si are both present. Self-aligned silicidation is also known in the art as “salicidation” and the self-aligned resultant metal compound has been referred to as “salicide.” In the illustrated arrangement, such locations have silicon exposed below the metal Ni layer. Thus, ideally, no silicide growth takes place at the position of the spacers 50 (FIG. 1C). While the top of the gate 10 is shown as exposed to the self-aligned silicidation process, in other arrangements only the source/drain regions are silicided and the gate can include a top insulation layer to prevent silicidation.
FIG. 1C schematically shows that the formation of the silicide film continues until the Ni film has been completely consumed in the regions above exposed silicon. Above the silicon there is no Ni left to react. This process, generally referred to as RTP1 for the first rapid thermal processing step, is generally conducted at temperatures in the range of about 300-400° C.
After this process is finished, the substrate is exposed to a selective metal etch (e.g., HCl, or piranha (H2SO4:H2O2) dip). In this wet etch process, the unreacted Ni is etched while the NiSix film remains intact (see FIG. 1D). This results in a low-resistivity silicide on top of the gate, source, drain and any other exposed silicon surfaces. By removing the unreacted Ni, these structures are electrically isolated from each other. Usually, a subsequent anneal (RTP2) at, e.g., 450° C. is applied to ensure conversion of any Ni2Si formed during silicidation to the lower resistivity phase NiSi.
Thus, in theory, the NiSix allows the formation of a conductive path with a low bulk resistivity and a good contact resistance. In practice, however, this process may not be effective in all contexts. For example, for certain semiconductor structures, such as a nonplanar multiple gate transistor, such as FinFETs, it may be desirable to form silicide on vertical walls, in addition to the tops of the gate, source, and drain regions. In other semiconductor devices, it may be beneficial to form silicide in narrow openings or trenches. The result is that the step coverage of the Ni over the three-dimensional structure is poor due, at least in part, to the limitations in the PVD processes used for depositing the Ni. Variation in thicknesses due to a non-uniform deposition of Ni creates variation in resistivity across the structures on the surface of a substrate. Such variation is undesirable because it can introduce non-uniformities in the electrical performance of electrical devices formed using the NiSix films.
While the above describes nickel silicide contact to silicon regions, the same principles apply to solid reaction of metals with semiconductor regions more generally.
In addition to its use in formation of conductive silicides, for example in advanced semiconductor devices and magnetic heads in hard drives, nickel films can also be used in other contexts, such as catalysts for carbon nanotube growth.
Depositing metal by more conformal processes like chemical vapor deposition (CVD) or atomic layer deposition (ALD) has not been straightforward. Accordingly, there is a need for methods of forming conformal nickel films as well as conformal metal-semiconductor compound films having more uniform resistivity on complex structures. Also there is a need to form ultrathin and uniform metal compound layers.